1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and method for fabricating the same and, more particularly, to a TFT formed by a Metal Induced Lateral Crystallization (MILC) process and method for fabricating the same.
2. Discussion of the Related Art
A polycrystalline silicon layer, which may be used for an active layer of a TFT, may be formed by depositing an amorphous silicon layer on an insulating substrate, and then crystallizing the layer using heat.
Solid Phase Crystallization (SPC) by means of thermal treatment, Eximer Laser Annealing (ELA) by means of laser crystallization, and Metal Induced Lateral Crystallization (MILC), or other like methods may be employed to crystallize the amorphous silicon layer.
The SPC method requires a high temperature for the crystallization, and the ELA method requires high-priced equipment, laser instability may produce temporal and spatial unevenness in the polycrystalline silicon, and the laser may cause striped defects.
On the other hand, with the MILC process, conventional thermal treatment equipment may be employed to perform crystallization at a relatively low processing temperature, and a laser is not required, which avoids laser-induced striped defects.
FIG. 1 is a plan view of a conventional TFT, which is limited to show an active layer 110 and a gate electrode 330 thereof.
The TFT shown in FIG. 1 comprises an active layer 110 having source/drain regions S and D and a channel region C, a gate electrode 140, and a contact hole 120 for exposing some portions of the source/drain regions S and D of the active layer 110. The active layer 100 is crystallized by an MILC process, and an MILC surface 130 may be formed at the center of the channel region C.
FIG. 2A, FIG. 2b, FIG. 2C and FIG. 2D show cross-sectional views, taken along the I-I′ line of FIG. 1, for explaining a method for fabricating the conventional TFT.
Referring to FIG. 2A, amorphous silicon is deposited on an insulating substrate 200 having a buffer layer 210, and it is patterned to form an active layer 220.
A gate insulating layer 230 and a gate electrode material are then sequentially formed on the substrate, and the gate electrode material is patterned to form a gate electrode 240.
Next, impurities are implanted in the active layer 220 using the gate electrode 240 as a mask to form source/drain regions 221 and 225. A region between the source/drain regions 221 and 225 acts as a channel region 223.
Referring to FIG. 2B, an interlayer insulating layer 250 is then deposited on the substrate, and contact holes 251 and 255 are formed to expose a portion of the source/drain regions 221 and 225.
A crystallization inducing metal layer 260, which may be formed of nickel (Ni), is then deposited on the substrate by means of sputtering or other similar methods.
Referring to FIG. 2C, the amorphous silicon layer of the active layer 220 may be heat treated in a furnace to form a polycrystalline silicon layer. The crystallization may be performed at a temperature of 550° C. and at a speed of 3 μm/hr.
In this case, the amorphous silicon of lower regions 221a and 225a is crystallized by the metal induced crystallization (MIC) process, and the remaining amorphous silicon regions 221b and 225b are crystallized by the MILC process.
Referring to FIG. 2D, the crystallization inducing metal layer 260 is then removed, and source/drain electrodes 271 and 275 are formed to form a TFT.
However, the channel region's electrical characteristics may affect the TFT's electrical characteristics. In the TFT formed as described above, an MILC surface, where crystals meet due to the MILC process, is formed within the channel region 223, and it may block a charge transfer, which will adversely affect the TFT's electrical characteristics.
Furthermore, in the heat treating process used to crystallize the active layer, the thermal treatment may take a long time at a constant temperature.